1. Field of the Invention
Embodiments of the present invention relate to a method of fabricating a semiconductor package, and a semiconductor package formed thereby.
2. Description of the Related Art
As the size of electronic devices continue to decrease, the associated semiconductor packages that operate them are being designed with smaller form factors, lower power requirements and higher functionality. Currently, sub-micron features in semiconductor fabrication are placing higher demands on package technology including higher lead counts, reduced lead pitch, minimum footprint area and significant overall volume reduction.
One branch of semiconductor packaging involves the use of a leadframe, which is a thin layer of metal on which one or more semiconductor die are mounted. The leadframe includes electrical leads for communicating electrical signals from the one or more semiconductors to a printed circuit board or other external electrical devices. Common leadframe-based packages include plastic small outlined packages (PSOP), thin small outlined packages (TSOP), shrink small outline packages (SSOP) and thin quad flat packages (TQFP). These packages include leads which extend out from the sides of the encapsulated package, which leads may be surface mounted to a host device such as a printed circuit board (PCB) as by soldering. Another common type of leadframe-based package is a leadless package. These include dual flat no-lead (DFN) and quad flat no-lead (QFN) packages. These packages do not have leads extending out of the sides of the package, but instead have exposed terminals at a bottom surface of the package for soldering to a host device such as a PCB. The leadframe package shown in FIGS. 1 and 2 may be used in either leaded (e.g., TSOP) or leadless (e.g., DFN) packages.
FIG. 1 shows a leadframe 20 before attachment of a semiconductor die 22. A typical leadframe 20 may include a number of leads 24 having first ends 24a for attaching to semiconductor die 22, and a second end (not shown) for affixing to a printed circuit board or other electrical component. Leadframe 20 may further include a die attach pad 26 for structurally supporting semiconductor die 22 on leadframe 20. While die attach pad 26 may provide a path to ground, it conventionally does not carry signals to or from the semiconductor die 22. In certain leadframe configurations, it is known to omit die attach pad 26 and instead attach the semiconductor die directly to the leadframe leads in a so-called chip on lead (COL) configuration.
Semiconductor leads 24 may be mounted to die attach pad 26 as shown in FIG. 2 using a die attach compound. Semiconductor die 22 is conventionally formed with a plurality of die bond pads 28 on at least first and second opposed edges on the top side of the semiconductor die. Once the semiconductor die is mounted to the leadframe, a wire bond process is performed whereby bond pads 28 are electrically coupled to respective electrical leads 24 using a delicate wire 30. The assignment of a bond pad 28 to a particular electrical lead 24 is defined by industry standard specification. FIG. 2 shows less than all of the bond pads 28 being wired to leads 24 for clarity, but each bond pad may be wired to its respective electrical lead in conventional designs. It is also known to have less than all of the bond pads wired to an electrical lead as shown in FIG. 2.
FIG. 3 shows a cross-sectional side view of leadframe 20 and semiconductor die 22 after the wire bond process. Once wire bonding is completed, a molding process is performed to encase the components in a molding compound 34 to form the finished package. It is known to recess or “down-set” the semiconductor die within the leadframe, as shown in FIG. 3, in order to balance the semiconductor die against the forces of the molding compound as it flows around the die and leadframe.
As shown in FIGS. 2 and 3, it is typical to have bond pads 28 on first and second opposite sides of the semiconductor die 22 for electrical coupling with their respective leads. According to industry specification and ease of design, bond pads 28 along the first edge of the semiconductor die connect to respective leadframe leads adjacent to the first edge of the semiconductor die, and bond pads along the second, opposite edge of the semiconductor die connect to respective leadframe leads adjacent to the second edge of the semiconductor die.
In an effort to reduce semiconductor die form factor, it is now known to provide bond pads on certain semiconductor die, such as for example ASIC controllers, along only one edge of the die, or two adjacent edges as shown in FIG. 4. A problem with such configurations is that four-sided leadframes generally do not have enough leads on a single side to accommodate all of the die bond pads along the edge of a die having pads along one or two edges (there would be more die bond pads along a side than is shown in FIG. 4).
It is currently known to provide a BGA (Ball Grid Array) package to connect to two-sided die. BGA packages provide the advantage that they have high pin-out density and are able to connect to each of the die bond pads in a flip-chip arrangement. However, BGA packages are expensive and not desirable for certain applications. It is therefore desirable to provide a four-sided leadframe capable of connecting to all of the die bond pads along one or two edges of a semiconductor die.